1. Field of the Invention
The present invention relates generally to a ball grid array. More specifically, the present invention relates to a ball grid array used in a flip-chip type on board semiconductor assembly.
2. State of the Art
Advances in semiconductor technology have facilitated the development of smaller integrated circuits having higher operating speeds. Presently, industry possesses technology to fabricate computers, telephones, scanners and video cameras and other electronic devices which can fit within a shirt pocket or similar space, at decreasing manufacturing costs and sales prices. Much of these size reductions and higher operating speeds have been facilitated by design of smaller and smaller semiconductor devices having a larger number of electrical connections for each semiconductor device.
With the miniaturization and increased operating speeds of semiconductor devices, packaging techniques are also being revised. Of the packaging techniques, much effort is being placed to keep up with the size reductions and operating speed increases of semiconductor devices utilizing chip on board (COB) assembly techniques. Among the COB techniques for attaching semiconductor devices to a printed circuit board are wire bonding, tap automated bonding (TAB), and flip-chip attachment.
In wire bonding, numerous wires are connected to contact pads on the semiconductor device and extend outwardly over the edges of the semiconductor device to correspond with contact pads on a substrate or printed circuit board. The process requires individual connections of each contact on the semiconductor device and requires an area of the substrate substantially larger that the semiconductor device itself. Also, due to the long lengths of the wire used to connect the chip to the printed circuit board and the resistance thereof, the speed at which the semiconductor device interacts with other circuitry is affected and, generally, is slower with longer lengths of wire.
In tape automated bonding or TAB, metallic leads are disposed on a polymeric tape. The leads may be connected individually or in mass to the contact pads of the semiconductor device and to the contact pads of the substrate. Unfortunately, like the wire bonding method, this method also requires utilizing a substantial area of the surface of the substrate. Also, depending upon the length of the metallic leads on the tape connected to the semiconductor device, the speed at which the semiconductor device interacts with other circuitry is affected and, generally, is slower as the length of the metallic leads increases.
On the other hand, flip-chip attachment techniques utilize the least amount of space and offer shorter interconnections with other circuitry for potentially increased interaction response, that is the space utilized on the substrate is substantially equal to the semiconductor device itself. In a flip-chip attachment technique, bond pads on the active surface of a semiconductor device may include an array of solder balls for mounting directly to a substrate, such as a printed circuit board, a carrier, and/or another semiconductor device. The array of solder balls on the semiconductor device is commonly referred to as a ball grid array (BGA). The BGA must be a mirror image of the connecting pads on the printed circuit board so that precise connection is made. With the solder balls arranged between the semiconductor device and substrate, electrical and mechanical connection is made thereto by reflowing the solder balls.
Of the three discussed COB techniques, a flip-chip type attachment technique is believed by some to be best suited to comply with the trend of the miniaturization and increased operating speeds of semiconductor devices. However, in comparison to the interconnect bumps in a BGA utilized elsewhere in semiconductor packaging (i.e., approximately 0.8 mm-1.3 mm diameter), the prior art interconnect bumps utilized in flip-chip assemblies are of a minute size (i.e., approximately 0.3 mm-0.8 mm diameter). Because of the minute size necessary for flip-chip packaging, the choice of metalization for the flip-chip assembly interconnect bumps is solder material or variations thereof, wherein the conventional interconnect bumps employed are bumps made entirely of solder material.
Although flip-chip attachment techniques utilize less space and are more responsive than other COB techniques, there are several problems associated with flip-chip packaging and the solder balls employed therein. Among the problems include the planarity of the substrate and the semiconductor die, which planarity of both effect the solder bumps and solder balls therebetween in providing sufficient electrical and mechanical connection. Compounding this difficulty of planarity is the difficulty of providing solder balls with a consistent solder ball diameter yielding a ball height. As a result of the planarity and solder bump and solder ball height problems, the solder bumps and solder balls often become deformed and marked in test sockets during reflow and burn-in testing due to the softness of the solder material. Also, the solder bumps and solder balls may become deformed during handling of the semiconductor device. Further, the solder bumps or solder balls may the knocked off or removed from one or more of the bond pads of the semiconductor device during handling. Consequently, the solder balls are often too deformed, too marked, or missing to provide sufficient electrical and mechanical connection in the final mounting of the semiconductor device to the substrate.
Furthermore, the solder material used for the solder bumps or solder balls may be selected for mechanical properties for attaching the semiconductor device to the substrate or printed circuit board, rather than being selected for having good electrical conductivity properties during service. As the operational speed of semiconductor devices is constantly increasing, it is more important that the material for the attachment of the semiconductor device to the substrate or printed circuit board be selected for electrical properties while having the ability to form mechanical connections having the desired characteristics.
Also, the use of solder balls and solder material on the bond pads of semiconductor devices and substrates requires the use of solder flux which can be difficult to apply and control in solder reflow operations to prevent damage to the semiconductor device and substrate. Therefore, as it is desirable to minimize the use of solder and solder flux for the formation of the connections between the semiconductor device and the substrate or printed circuit board to which it is attached.
In U.S. Pat. No. 2,934,685 illustrated is a ball or sphere of having a diameter on the order 0.005 inches is made from an inert material, such as tungsten or molybdenum, coated with a layer of gold containing antimony, is attached to a semiconductor wafer, having a layer of aluminum subsequently applied thereto and the semiconductor body with the heating of the ball or sphere to cause the aluminum to penetrate the upper layer of the semiconductor body causing it to be converted to p-type conductivity.
In U.S. Pat. No. 3,496,428 illustrated is a metal contact 6 comprising a preliminary metallizing layer of gold nickel on the surface of the p-type region of a semiconductor wafer substrate and a silver dot in the shape of a somewhat hemispherical ball alloyed to the metal layer. A nickel layer is subsequently deposited on the silver dot.
In U.S. Pat. No. 5,841,198 illustrated is a ball grid array package utilizing solder balls having central cores of a material with a higher melting point than solder material surrounding the core. When the ball grid package and motherboard assembly are heated to the melting point of the solder material, the cores of the solder balls remain solid and function as spacers in preventing direct contact of the package surface and the motherboard surface. The core of the solder ball can comprise a lead tin alloy having a higher melting point than conventional solder, such as 90% lead and 10% tin by weight which melts at approximately 290xc2x0 C. or, alternately, may comprise copper. The solid core of the solder ball can be plated onto the solid core, or the solid core can be dipped in liquid solder with surface tension coating the core material.
In U.S. Pat. No. 5.971,253 illustrated is a microelectronic element assembly such as a semiconductor chip assembly using a connection component incorporating a dielectric sheet with electrically conductive elements therein. Each electrically conductive element may include flexible body and a flexible conductive shell.
In U.S. Pat. No. 5,736,790 illustrated is bump formed on a pad which is provided on either a semiconductor chip or a package or a wiring substrate for input or output thereof. The bump includes a projection projecting form the pad, a ball having conductivity and located above the pad, and a conductive bonding material for bonding the pad and the ball, wherein the creep strength of the ball is larger than the strength of the conductive bonding material.
In U.S. Pat. No. 5,808,853 illustrated is a capacitor having a multilevel interconnection technology using at least one solder ball reflowed and secured onto the capacitor. The solder ball is in electrical communication with the capacitor through a contact. On the reflowed solder ball a cap of low melting point metal is secured.
In U.S. Pat. No. 5,989,937 illustrated is a method for compensating for bottom warpage of a ball grid array (BGA) integrated circuit. The solder balls arrayed on the bottom surface of a package of the integrated circuit provide for surface mounting of the integrated circuit by solder reflow. The solder balls are planarized to compensate individually for warpage of the integrated circuit package by variations in the individual dimensions of dependency of each solder ball below the bottom surface of the package.
In U.S. Pat. No. 5,400,950 illustrated is a method for controlling solder bump height for flip chip integrated circuit devices. The method of controlling the height of the solder bumps involves the use of non-input/output, or dummy solder bumps which are present in sufficient numbers to overcome the tendency for the input/output solder bumps to draw the flip chip excessively close to the circuit board. Because the dummy solder bumps are electrically inactive, their height can be governed by electrically isolate pads on the surface of the circuit board.
In U.S. Pat. No. 5,903,058 illustrated is a method for forming under bump metallurgy pads and solder bump connections for a flip chip. The method employs a sloped-wall via for the formation of the under bump metallurgy since sloped edges or walls of a via assist in forming the spherical solder ball when the initially-deposited solder is heated.
In U.S. Pat. No. 3,809,625 illustrated are silver bumps electroplated on gold pads until the bump height reaches a range of 0.5 to 1.5 mils resulting in a bump width of 7 to 8 mils. Then a gold plating is applied to the silver bumps. The bumps may also be formed of solder containing ten percent (10%) by weight tine and ninety percent (90%) by weight lead.
In U.S. Pat. No. 4,600,600 illustrated are a thin metallic layers used as an adhesion layer and diffusion barrier between lead contacts formed of electro-deposited copper and the chip-internal interconnects of a semiconductor circuit or substrate.
In U.S. Pat. No. 5,461,261 illustrated is a semiconductor chip provided with bumps formed of alternating layers of gold and tin by electroplating or vacuum evaporation, the gold and tin layers being capable of eutectic reaction. The gold and tin layers are deposited on a layer of tungsten and titanium formed on a layer of aluminum. The formation of the bumps by the electroplating of gold and tin results in the bumps having a slight disparity in the bump height.
In U.S. Pat. No. 5,640,052 illustrated are the pads of a semiconductor chip and pads of a substrate connected to each other by solder bumps having an hourglass shape, each solder bump including a metal core and solder reflowed thereover.
In U.S. Pat. No. 5,506,756 illustrated is a ball grid array (BGA) package which contains an integrated circuit die mounted on flexible polyamide tape material. The conductors on the flexible polyimide tape material and the bond pads on the second surface of the integrated circuit die have solder balls attached thereto for connection to a printed circuit board. The solder balls are preferably constructed from a relatively resilient material, such as a 60:40 lead-time composition, 62:32:2 lead-time-silver composition or an indium alloy to withstand the stresses created within the solder joints with the printed circuit board.
In U.S. Pat. No. 5,334,857 illustrates a semiconductor device provided with solder balls which are electrically coupled to portions of a semiconductor die necessary for operation. The solder balls are preformed for attachment to conductive pads or terminals on the substrate having a semiconductor device wire bonded thereto.
In U.S. Pat. No. 5,468,995 illustrates the use of compliant polymer columnar I/O connections on the bottom of a substrate to accommodate thermally induced stress during semiconductor device operation connected to the upper side of the substrate.
Therefore, based on the foregoing, it would be advantageous to develop a BGA wherein the interconnect bumps substantially overcome the problems associated with the conventional solder balls used in flip-chip packaging.
The present invention relates to a method and apparatus for providing a BGA that electrically and mechanically interconnects a semiconductor device to a substrate for flip-chip packaging. The present invention is directed to a method and apparatus for providing a plurality of balls in a BGA, of which the plurality of balls are substantially uniform in height. The method and apparatus provide a plurality of balls in a BGA that substantially obtains proper electrical connection between a semiconductor device and substrate for flip-chip packaging. The method and apparatus of the present invention provide a plurality of balls in a BGA, wherein the bumps include a core material and a thin outer layer of a different material than that of the core material. In the present invention, the core material has greater rigidity than the material of the outer layer. Further, the core material has a higher melting temperature than the material of the outer layer.
In one embodiment of the present invention, the core material is a conductive material having a thin layer of another conductive material thereover as an outer layer. In a second embodiment of the present invention, the core material is a non-conductive polymeric material having a thin layer of conductive material thereover as an outer layer. Alternatively, the core material is a conductive polymeric material or a composite material. In a third embodiment of the present invention, the core material is a conductive material having a thin outer layer of solder material.
In each embodiment of the present invention the use of a solid core having a thin layer of another metal or solder thereover allows the reflow soldering of the semiconductor device to the substrate without the use of additional solder or solder flux being applied to either the present invention or the solder located on the bond pads of the semiconductor device or located on the contact pads of the substrate.
The method and apparatus of the present invention utilizing balls with a core material and an outer layer may be used to connect any type of semiconductor device, bare or packaged, to any type of substrate by flip-chip methods. Further, the method and apparatus of the present invention utilizing balls with a core material and an outer layer may be used to stack multiple semiconductor devices to one another by also using the flip-chip techniques.